Flash memory devices are non-volatile memory devices which allow information to be electrically erased or programmed. Flash memory devices are widely employed as memory devices for electronic devices such as computers, and digital cameras. A unit cell gate pattern of a flash memory device may include a floating gate used as a charge storage layer, and a control gate used to control input and output signals. The floating gate is separated from a semiconductor substrate by a tunnel oxide layer, and the floating gate and the control gate are separated from each other by an inter-gate dielectric layer. The inter-gate dielectric layer electrically isolates the floating gate from the control gate so that the floating gate may serve as a charge storage layer.
The floating gate and the control gate may be formed of polysilicon layers. The inter-gate dielectric layer may be an ONO layer (silicon oxide layer/silicon nitride layer/silicon oxide layer). As densities of flash memory devices increase, a reduced resistance gate pattern and an improved inter-gate dielectric layer to replace the ONO layer may be desired. For example a metal layer may be deposited on the polysilicon layer to provide a reduced resistance gate pattern for the control gate. A tungsten layer, a titanium layer, or a tantalum layer having a relatively low specific resistance and a relatively high melting point may be used for the metal layer. The ONO layer for the inter-gate dielectric layer may be replaced with a high-k dielectric layer.
A dry etching process, such as plasma etching or reactive ion etching (RIE), may be used to form the gate pattern of the semiconductor device. When a gate pattern is formed using a dry etching process, a corner of a gate oxide layer below the gate pattern may be damaged by etching. The etch damage may affect a dielectric breakdown voltage of the gate oxide layer below the gate pattern reducing reliability of the semiconductor device. Accordingly, to cure the etch damage of the gate oxide layer, an additional oxidation process (referred to as a reoxidation process) may be carried out after the gate pattern is formed. An example of the reoxidation process is disclosed in U.S. Pat. No. 6,372,618 the disclosure of which is hereby incorporated herein in its entirety by reference.
A reoxidation process may be carried out during the process of forming the gate pattern of the flash memory device to cure etch damage of the tunnel oxide layer. The reoxidation process may be performed at a relatively high temperature of about 850° C. (degrees C.) or more, and oxidants may penetrate through an interface between the inter-gate dielectric layer and the floating gate and an interface between the inter-gate dielectric layer and the control gate so that a bird's beak is formed at both sides of the inter-gate dielectric layer. When the thickness of the inter-gate dielectric layer increases due to the bird's beak, a dispersion of cell characteristics of the flash memory device may increase. When a high-k dielectric layer is used as the inter-gate dielectric layer as described above, the floating gate and the control gate may be contaminated by metal ions diffusing from the high-k dielectric layer during the reoxidation process.
To address these issues, a silicon nitride layer spacer may be formed covering sidewalls of the gate pattern, and then, the reoxidation process may be performed. A leakage current, however, may occur between the floating gate and the insulating gate along an interface between the gate pattern and the silicon nitride layer spacer.